This invention relates generally to output buffer circuits and more particularly, it relates to a high-speed, high-drive output buffer circuits in integrated circuits.
As is well-known, digital logic circuits are widely used in the areas of electronics and computer-type equipment. One such use of digital logic circuits is to provide an interface function between one logic type of a first integrated circuit device and another logic type of a second integrated circuit device. An output buffer circuit is an important component for performing this interface function. The output buffer circuit generates, when enabled, an output signal which is a function of a data signal received from other logic circuitry of the integrated circuit.
Output buffer circuits typically use a pull-up transistor device and a pull-down transistor device connected in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive potential VCC, which is connected to an internal power supply potential node. A second power supply terminal may be supplied with a ground potential, which is connected to an internal ground potential node. The connection point of the pull-up and pull-down devices is further joined to an output terminal.
Dependent upon the logic state of the data input signal and an enable signal, either the pull-up or pull-down transisted device is quickly turned ON and the other one of them is turned OFF. Such rapid switching ON and OFF of the pull-up and pull-down transistor devices causes sudden surges of current creating what is commonly known as current spikes. Also, during output switching, charging and discharging currents from the pull-up and pull-down transistors to the external capacitance load exist. These transient currents (current spikes and charging/discharging currents) will flow through the impedance and inductive components of power supply and ground lines so as to cause inductive noises at the internal power supply potential and the internal ground potential nodes of the output buffer.
These internal supply and ground noises are undesirable, and they will degrade the output logic "1" and logic "0" voltage levels causing interfacing problems among the output buffer circuit and other integrated circuits. This undesirable supply and ground noise is generally referred to as "ground bounce." The "ground bounce" will be more severe when more output buffers are switching simultaneously, at higher operating speed, or driving larger external capacitance loads.
In the design of output buffer circuits, it is thus seen that a trade-off exists between achieving high-speed/high-drive operation and minimizing of the ground bounce. While there have been attempts made in the prior art of output buffer design to achieve higher speed and higher output drive currents by increasing the sizes of the output pull-up and pull-down devices, this has resulted in the disadvantage of increasing the ground bounce. In other words, in order to minimize the ground bounce for prior art output buffer circuit design, the high-speed or high-drive needed to be sacrificed.
It would therefore be desirable to provide an output buffer circuit which has reduced ground bounce, but yet maintains a high speed of operation and has a high drive current capability. The output buffer circuit of the present invention includes an AC buffer and a DC buffer. The AC buffer is formed of a first pull-up transistor and a first pull-down transistor. The DC buffer is formed of a second pull-up transistor and a second pull-down transistor. The sizes of the first pull-up and pull-down transistors in the AC buffer are smaller in size than the second pull-up and pull-down transistors in the DC buffer. The reduction in ground bounce is achieved by delaying the turn-on of the second larger pull-up and pull-down transistors with respect to the first pull-up and pull-down transistors during transitions.